The present trend in semiconductor technology is toward large scale integration of devices with very high speed and low power performance. The parameters that are essential to such high performance bipolar transistors include the presence of low parasitic capacitances as realized by shallow vertical junctions, and small horizontal geometries. In other words, it is necessary to make the devices in the integrated circuits as small as possible in both the horizontal and vertical directions.
One approach developed to reduce the size of integrated circuits is the use of trench or slot isolation to isolate adjacent bipolar structures. This technique incorporates etching grooves into the semiconductor wafers adjacent to those regions in which PN junctions are to be formed. Thus, the substrate layers are made relatively shallow in order to minimize the depth to which the groove must be etched.
Also in such devices, it is important to be able to form a substrate tap; that is, a contact from the substrate to the most negative potential available, typically the negative side of the power supply. In a typical bipolar device, the substrate is a P-type material formed with a buried layer of N+ material and an N-type epi region on top. The active devices will be formed in tubs; i.e., isolated regions of the N-type epi material. By tying the substrate to the most negative potential in the circuit, the P-type substrate is negatively biased, which will reverse bias all the N-epi tubs. The N+ buried layers and the N-type epi tubs will be more positively biased, i.e., a more positive potential than the substrate, thereby isolating the tubs one from another.
Tying the substrate to the most negative potential in the circuit means that the PN junctions formed by the P substrate and the N-type buried layer are reverse biased. In this way, isolation is maintained on the floor of all devices by what are essentially reverse biased diodes.
An example of the importance of this follows from considering the effect of having bipolar memory elements that include, for example, lateral PNP transistors that can inject current into the substrate through the parallel vertical PNP devices whose collector is the substrate. The circuit designer needs to keep the substrate from biasing or floating upward. The more negative the substrate is with respect to the active devices, the less capacitance is present. This is because of the isolation provided by the depletion region of the P substrate, which widens with higher levels of reverse bias, where the buried layer is reversed biased with respect to the P-type substrate. The depletion region of the P substrate is acting as an insulator, as the PN junction between the substrate and the buried layer is reverse biased.
Returning to the example of a bipolar memory using lateral PNP loads, such a lateral PNP has horizontally adjacent P, N and P regions. Holes are injected from the P-type emitter of the memory cell into the N-epi base of the lateral PNP; the P-type substrate can act as a parallel collector and collect holes as well as the adjacent lateral P-type collector. The buried layer is provided to suppress the vertical injection of hole currents into the substrate. If a large memory array has been formed, and the cells, collectively, are permitted to inject current into the substrate, a large cumulative current can be created in the substrate. This injected charge must be carried off, or the P-type substrate will drift up to such an extent that the array essentially has forward bias across the PN junctions. In this forward bias condition, the entire array can essentially cease functioning. Maintaining the depletion region as wide as possible at the PN junction between the substrate and the buried layer by carrying off the injected charge is essential in minimizing collector-substrate capacitance. In the absence of successfully tying the substrate to the most negative point in the circuit, the substrate can forward bias, and as it forward biases N-type epi tubs nearer to Vcc, parasitic lateral NPN devices can also turn on. This can induce several kinds of phenomena, ranging from minor performance degradation to functional failure and/or latch-up.
A related problem, in the absence of successfully tying the substrate to the point of negative potential, is that the substrate is floating and it is possible to capacitively couple AC signals into the substrate. This injection of carriers can cause cross-talk to critical circuit nodes which can cause serious problems ranging from loss of noise immunity to the circuit breaking into oscillations.
The ability to tie the substrate to the point of most negative potential is also essential in forming TTL devices.
While this problem has previously been recognized, the substrate taps known in the art largely relied on additional masking steps to form the tap. Typically, the buried layer is masked to define a region through the N epi and the N buried layer. Then a slug of P-type material is defined through the buried layer to the substrate, so that a contact can be formed via this P-type slug to the P-type substrate.